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256 - position spi/i 2 c selectable digital potentiometer data sheet ad5161 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is a ssumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2003 C 2012 analog devices, inc. all rights reserved. features 256- position end - to - end resistance 5 k?, 10 k?, 50 k?, 100 k? compact msop - 10 (3 mm 4.9 mm) package pin selectable spi/i 2 c compatible interface extra package address decode pin ad0 full read/write of wiper register power - on preset to midscale si ngle supply 2.7 v to 5.5 v low temperature coefficient 45 ppm/c low power, i dd = 8 a wide operating temperature ? 40 c to +125c sdo output allows multiple device daisy - chaining evaluation board available applications mechanical potentiometer replacement in new designs transducer adjustment of pressure, temperature, position, chemical, and optical sensors rf amplifier biasing gain control and offset adjustment general description the ad5161 provides a compact 3 mm 4.9 mm packaged solution for 256 - positi on adjustment applications. these devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid - state reliability, and superior low temperature coefficient performance. the wiper settings are controllable through a pin selectable spi or i 2 c compatible digital interface, which can also be used to read back the wiper register content. when the spi mode is used, the device can be daisy - chained (sdo to sdi), allowing several parts to share the same control lines. in the i 2 c mode, address pin ad0 can be used to place up to two devices on the same bus. in this same mode, command bits are available to reset the wiper position to midscale or to shut down the device into a state of zero pow er consumption. operating from a 2.7 v to 5.5 v power supply and consuming less than 5 a allows for usage in portable battery - operated applications. functional block dia gram wiper register sdi/sda clk/scl dis cs/ad0 gnd sdo/nc v dd a w b spi or i 2 c interface figure 1. pin configuration 1 2 3 4 5 10 9 8 7 6 a b cs/ado sdo/nc sdi/sda dd ad5161 top view (not to scale) w v dis gnd clk/scl figure 2.
ad5161 data sheet rev. b | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general d escription ......................................................................... 1 functional block diagram .............................................................. 1 pin configuration ............................................................................. 1 revi sion history ............................................................................... 2 electrical characteristics 5 k? version ...................................... 3 electrical characteristics 10 k?, 50 k?, 100 k? versions ....... 4 timing characteristics 5 k? , 10 k?, 50 k?, 100 k? versions 5 absolute maximum ratings 1 .......................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 test circuits ..................................................................................... 12 spi interface .................................................................................... 13 i 2 c interface .................................................................................... 14 theory of operation ...................................................................... 15 programming the variable resistor ......................................... 15 programming the potentiometer divider ............................... 16 pin sele ctable digital interface ................................................. 16 level shifting for bidirectional interface ................................ 18 esd protection ........................................................................... 18 terminal voltage operating range ......................................... 18 power - up sequence ................................................................... 18 layout and power supply bypassing ....................................... 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 8/12 rev. a to rev. b changes to applicati ons section .................................................... 1 updated outline dimensions ....................................................... 19 4/09 rev. 0 to rev. a changes to ordering guide .......................................................... 19 5/03 revision 0: initial version
data sheet ad5161 rev. b | page 3 of 20 electrical character istics 5 k ? version v dd = 5 v 10%, or 3 v 10%; v a = +v dd ; v b = 0 v; C 40c < t a < +125c; unless otherw ise noted. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r - dnl r wb , v a = no connect ? 1.5 0.1 +1.5 lsb resistor integral nonlinearity 2 r - inl r wb , v a = no connect C 4 0.75 +4 lsb nominal resistor tolerance 3 ?r ab t a = 25c C 30 +30 % resistance temperature coefficient ?r ab /?t v ab = v dd , wiper = no connect 45 ppm/c wiper resistance r w 50 120 ? dc characteristics p otentiometer divider mode (specifications apply to all vrs) resolution n 8 bits differential nonlinearity 4 dnl C 1.5 0.1 +1.5 lsb integral nonlinearity 4 inl C 1.5 0.6 +1.5 lsb voltage divider temperature coefficien t ?v w /?t code = 0x80 15 ppm/c full - scale error v wfse code = 0xff C 6 C 2.5 0 lsb zero - scale error v wzse code = 0x00 0 +2 +6 lsb resistor terminals voltage range 5 v a,b,w gnd v dd v capacitance 6 a, b c a,b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i dd_sd v dd = 5.5 v 0.01 1 a common - mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic h igh v ih 2.4 v input logic low v il 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies po wer supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3 8 a power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 0.2 mw power supply sensitivity pss ?v dd = +5 v 10%, code = midscale 0.02 0.05 %/% dynamic chara cteristics 6 , 9 bandwidth C 3db bw_5k r ab = 5 k?, code = 0x80 1.2 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.05 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 2.5 k?, rs = 0 6 nv/hz
ad5161 data sheet rev. b | page 4 of 20 electrical character istics 10 k ?, 50 k ?, 100 k ? versions v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; C 40c < t a < +125c; unless otherwise noted. table 2 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r - dnl r wb , v a = no connect C 1 0.1 +1 lsb resistor integral nonl inearity 2 r - inl r wb , v a = no connect C 2 0.25 +2 lsb nominal resistor tolerance 3 ?r ab t a = 25c C 30 +30 % resistance temperature coefficient ?r ab /?t v ab = v dd , wiper = no connect 45 ppm/c wiper resistance r w v dd = 5 v 50 120 ? dc characteristics potentiometer divider mode (specifications apply to all vrs) resolution n 8 bits differential nonlinearity 4 dnl C 1 0.1 +1 lsb integral nonlinearity 4 inl C 1 0.3 +1 lsb voltage divider temperature coefficient ?v w /?t code = 0x80 15 ppm/c full - scale error v wfse cod e = 0xff C 3 C 1 0 lsb zero - scale error v wzse code = 0x00 0 1 3 lsb resistor terminals voltage range 5 v a,b,w gnd v dd v capacitance 6 a, b c a,b f = 1 mhz, measured to gnd, code = 0x80 45 p f capacitance 6 w c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i dd_sd v dd = 5.5 v 0.01 1 a common - mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outp uts input logic high v ih 2.4 v input logic low v il 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3 8 a power dissipation 8 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 0.2 mw power supply sensitivity pss ?v dd = +5 v 10%, code = midscale 0.02 0.05 %/% dynamic characteristics 6 , 9 bandwidth C 3db bw r ab = 10 k?/50 k?/100 k?, code = 0x80 600/100/40 khz total harmonic distortion thd w v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.05 % v w settling time (10 k?/50 k?/100 k?) t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k?, rs = 0 9 nv/hz
data sheet ad5161 rev. b | page 5 of 20 timing characteristi cs5 k ?, 10 k ?, 50 k ?, 1 00 k ? versions v dd = +5v 10%, or +3v 10%; v a = v dd ; v b = 0 v; C 40c < t a < +125c; unless otherwise noted. table 3 . parameter symbol conditions min typ 1 max unit spi interface timing characteristics 6 , 10 (specifications apply to all parts) clock frequency f clk 25 mhz input clock pulsewidth t ch , t cl clock level high or low 20 ns data setup time t ds 5 ns data hold time t dh 5 ns cs se tup time t css 15 ns cs high pulsewidth t csw 40 ns clk fall to cs fall hold time t csh0 0 ns clk fall to cs rise hold time t csh1 0 ns cs rise to clock ris e setup t cs1 10 ns i 2 c interface timing characteristics 6 , 11 (specifications apply to all parts) scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start ) t 2 after this period, the first clock pulse is generated. 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 50 s t su;sta setup time for repeated start condition t 5 0.6 s t hd; dat data hold time t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s notes 1 typical spec ifications represent average readings at +25c and v dd = 5 v. 2 resistor position nonlinearity error r - inl is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. parts are guaranteed monotonic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output d/a converter. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 resistor terminals a, b, w have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production t est. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 9 all dynamic characteristics use v dd = 5 v. 10 see timing diagram for location of measured values. all input control voltages are specified with t r = t f = 2 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. 11 see timing diagrams for locations of measured values.
ad5161 data sheet rev. b | page 6 of 20 absolute maximum rat ings 1 t a = 25c, unless otherwise noted. table 4 . parameter value v dd to gnd C 0.3 v to +7 v v a , v b , v w to gnd v dd i max 1 20 ma digital inputs and output voltage to gnd 0 v to +7 v operating temperature range C 40c to +125c maximum junction temperat ure (t jmax ) 150c storage temperature range C 65c to +150c lead temperature (soldering, 10 sec) 300c thermal resistance 2 ja (10 - lead msop) 200c/w notes 1 maximum terminal current is bounded by the maximum current handling of the switches, maximu m power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation = (t jmax C t a )/ ja . stresses above those listed under absolute maximum ratings may cause perman ent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating condition s for extended periods may affect device reliability. esd caution
data sheet ad5161 rev. b | page 7 of 20 pin configuration an d function descripti ons 1 2 3 4 5 10 9 8 7 6 a b cs/ado sdo/nc sdi/sda dd ad5161 top view (not to scale) w v dis gnd clk/scl figure 3 . pin configuration table 5 . pin function description pin o. mnemonic des cription 1 a a terminal. 2 b b terminal. 3 cs /ad0 chip select ( cs ) input, active low. when cs returns high, data will be loaded into the dac register. programmable address bit 0 (ad0) for multiple package decoding. 4 sdo/nc serial data output (sdo). open - drain transistor requires pull - up resistor. no connect (nc). 5 sdi/sda serial data input (sdi). serial data input/output (sda). 6 clk/scl serial clock input. positive edge tri ggered. 7 gnd digital ground. 8 dis digital interface select (spi/i 2 c select). spi when dis = 0, i 2 c when dis = 1. 9 v dd positive power supply. 10 w w terminal.
ad5161 data sheet rev. b | page 8 of 20 typical performance characteristics code (decimal) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 32 0 96 64 128 160 192 224 256 rheostat mode inl (lsb) 0.8 5v 3v figure 4. r - inl vs. code vs. supply voltages 5v 3v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 rheostat mode dnl (lsb) 0.8 code (decimal) 32 0 96 64 128 160 192 224 256 figure 5. r - dnl vs. code vs. supply voltages _ 40 c +25c +85c +125c ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 potentiometer mode inl (lsb) 0.8 code (decimal) 32 0 96 64 128 160 192 224 256 figure 6 . inl vs. code, v dd = 5 v code (decimal) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 32 0 96 64 128 160 192 224 256 potentiometer mode dnl (lsb) 0.8 ?40 c +25c +85c +125c figure 7 . dnl vs. code, v dd = 5 v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 potentiometer mode inl (lsb) 0.8 code (decimal) 32 0 96 64 128 160 192 224 256 5v 3v figure 8 . inl vs. code vs. supply voltages 5v 3v code (decimal) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 32 0 96 64 128 160 192 224 256 potentiometer mode dnl(lsb) 1.0 figure 9 . dnl vs. code vs. supply voltages
data sheet ad5161 rev. b | page 9 of 20 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 rheostat mode inl (lsb) 0.8 code (decimal) 32 0 96 64 128 160 192 224 256 c +25c +85c + 1 2 5 c ?40 figure 10 . r - inl vs. code, v dd = 5 v ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 1.0 rheostat mode dnl (lsb) 0.8 code (decimal) 32 0 96 64 128 160 192 224 256 _ 40c +25c +85c +125c figure 11 . r - dnl vs. code, v dd = 5 v temperature (c) 0 40 80 120 ?40 0 1.5 fse, full-scale error (lsb) 0 40 80 120 ?40 1.0 2.5 v dd = 5.5v v dd = 2.7v 2.0 0.5 figure 12 . full - scale error vs. temperature 0 40 80 120 ?40 0 1.5 zse, zero-scale error ( a) temperature (c) 0 40 80 120 ?40 1.0 2.5 v dd = 5.5v v dd = 2.7v 2.0 0.5 figure 13 . zero - scale error vs. temperature temperature (c) 0 40 80 120 ?40 0.1 1 10 i dd supply current (a) v dd = 5.5v v dd = 2.7v figure 14 . supply current vs. temperature i a shutdown current (na) temperature ( c ) 0 0 70 20 10 30 40 50 60 40 80 120 ?40 v dd = 5v figure 15 . shutdown curre nt vs. temperature
ad5161 data sheet rev. b | page 10 of 20 code (decimal) ?50 0 50 100 150 200 32 0 96 64 128 160 192 224 256 rheostat mode tempco (ppm/ c) figure 16 . rheostat mode tempco ?r wb /?t vs. code code (decimal) ?20 0 20 40 60 80 100 120 140 160 32 0 96 64 128 160 192 224 256 potentiometer mode tempco (ppm/ c) figure 17 . potentiometer mode tempco ?v wb /?t vs. code 1k 10k 100k 1m 0 ?6 ? 12 ? 18 ? 24 ? 30 ? 36 ? 42 ? 48 ? 54 ? 60 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 1 000 000.000hz mag (a/r) ?8.918db start 1 000.000hz stop 1 000 000.000hz figure 18 . gain vs. frequency vs. code, r ab = 5 k? 1k 10k 100k 1m 0 ? 6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 510 634.725hz mag (a/r) ?9.049db start 1 000.000hz stop 1 000 000.000hz figure 19 . gain vs. frequency vs. code, r ab = 10 k? 1k 10k 100k 1m 0 ?6 ?12 ?18 ?24 ?30 ?36 ?42 ?48 ?54 ?60 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 100 885.289hz mag (a/r) ?9.014db start 1 000.000hz stop 1 000 000.000hz figure 20 . gain vs. frequency vs. code, r ab = 50 k? 1k 10k 100k 1m 0 ?6 ? 12 ? 18 ? 24 ? 30 ? 36 ? 42 ? 48 ? 54 ? 60 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01 ref level 0.000db /div 6.000db marker 54 089.173hz mag (a/r) ?9.052db start 1 000.000hz stop 1 000 000.000hz figure 21 . gain vs. frequency vs. code, r ab = 100 k?
data sheet ad5161 rev. b | page 11 of 20 10k 100k 1m 10m ?5.5 ?6.0 ?6.5 ?7.0 ?7.5 ?8.0 ?8.5 ?9.0 ?9.5 ?10.0 ?10.5 ref level ?5.000db /div 0.500db start 1 000.000hz stop 1 000 000.000hz r = 5k? r = 10k? r = 50k? r = 100k? 5k? ? 1.026 mhz 10k? ? 511 mhz 50k? ? 101 mhz 100k ? ? 54 mhz figu re 22 . C 3 db bandwidth @ code = 0x80 frequency (hz) 10k 100 100k 1m 1k 0 20 40 60 psrr (db) code = 0x80, v a = v dd , v b = 0v psrr @ v dd = 3v dc 10% p-p ac psrr @ v dd = 5v dc 10% p-p ac figure 23 . psrr vs. frequency i dd (a) frequency (hz) 10k 800 700 600 500 400 300 900 200 100 100k 1m 10m 0 code = 0x55 code = 0xff v dd = 5v figure 24 . i dd vs. frequency vw clk ch 1 200mv b w ch 2 5.00 v b w m 100ns a ch2 3.00 v 1 2 figure 25 . digital feedthrough vw cs ch 1 100mv b w ch 2 5.00 v b w m 200ns a ch1 152mv 1 2 v a = 5v v b = 0v figure 26 . midscale glitch, code 0x80 C 0x7f vw cs ch 1 5.00v b w ch 2 5.00 v b w m 200ns a ch1 3.00 v 1 2 v a = 5v v b = 0v figure 27 . large signal settling time, code 0xff C 0x00
ad5161 data sheet rev. b | page 12 of 20 test circuits figure 28 to figure 36 illustrate the test circuit s that define the test conditions used in the product specification tables. v ms a w b dut v + = v dd 1lsb = v + / 2 n v+ figure 28 . test circuit for potentiometer divider nonlinearity error (inl, dnl) no connect i w v ms a w b dut figure 29 . test circuit for resistor posit ion nonlinearity error (rheostat operation; r - inl, r - dnl) v ms1 i w = v d d / r nominal v ms2 v w r w = [v ms1 ? v ms2 ] / i w a w b dut figure 30 . test circuit for wiper resistance ?v ?v ?v ?v ms % dd % pss (% / %) = v + = v dd 10% psrr (db) = 20 log ms dd ( ) v dd v a v ms a w b v + figure 31 . test circuit for power supply sensitivity (pss, pssr) op279 w 5v b v out offset gnd offset bias a dut v in figure 32 . test circuit for inverting gain b a v in op279 w 5v v out offset gnd offset bias dut figure 33 . test circuit for noninverting gain +15v ?15v w a 2.5v b v out offset gnd dut ad8610 v in figure 34 . test circuit for gain vs. frequency w b v ss to v dd dut i sw code = 0x00 r sw = 0.1v i sw 0.1v figure 35 . test circuit for incr emental on resistance w b v cm i cm a nc gnd nc v ss v dd dut nc = no connect figure 36 . test circuit for common - mode leakage c urrent
data sheet ad5161 rev. b | page 13 of 20 spi interface table 6 . ad5161 serial data - word format b7 b6 b5 b4 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb 2 7 2 0 sdi clk cs vout 1 0 1 0 1 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 rdac register load figure 37 . spi interface timing diagram (v a = 5 v, v b = 0 v, v w = v out ) t csho t css t cl t ch t ds t csw t s t cs1 t csh1 t ch sdi clk cs vout 1 0 1 0 1 0 v dd 0 1lsb (data in) dx dx figure 38 . spi interface detailed timing diagram (v a = 5 v, v b = 0 v, v w = v out )
ad5161 data sheet rev. b | page 14 of 20 i 2 c interface table 7 . write mode s 0 1 0 1 1 0 ad0 w a x rs sd x x x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte table 8 . read mode s 0 1 0 1 1 0 ad0 r a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte data byte s = start condition p = stop condition a = acknowledge x = dont care w = write r = read rs = reset wiper to midscale 80 h sd = shutdown connects wiper to b terminal and open circuits a terminal. it does not change contents of wiper register. d7, d6, d5, d4, d3, d2, d1, d0 = data bits . t 1 t 3 t 4 t 2 t 7 t 8 t 9 p s p s t 10 t 5 t 9 t 8 scl sda t 2 t 6 figure 39 . i 2 c interface detailed timing diagram scl frame 1 frame 2 start b master ack b ad5161 slave address bte stop b master instruction bte sda 0 1 0 1 1 0 ad0 r/w x rs x x x x x 1 9 1 9 d7 d6 d5 d4 d3 d2 d1 d0 ack b ad5161 frame 3 data bte 1 9 ack b ad5161 sd figure 40 . writing to the rdac register no ack b master scl sda 0 1 0 1 1 0 ad0 r/w d7 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 frame 1 frame 2 start b master ack b ad5161 slave address bte rdac register stop b master fig ure 41 . reading data from a previously selected rdac register in write mode
data sheet ad5161 rev. b | page 15 of 20 theory of operation the ad5161 is a 256-position digitally controlled variable resistor (vr) 1 device. an internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. programming the variable resistor rheostat operation the nominal resistance of the rdac between terminals a and b is available in 5 k, 10 k, 50 k, and 100 k. the final two or three digits of the part number determine the nominal resistance value, e.g., 10 k = 10; 50 k = 50. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal, plus the b terminal contact. the 8-bit data in the rdac latch is decoded to select one of the 256 possible settings. assume a 10 k part is used, the wipers first connection starts at the b terminal for data 0x00. since there is a 60 wiper contact resistance, such connection yields a minimum of 60 resistance between terminals w and b. the second connection is the first tap point, which corresponds to 99 (r wb = r ab /256 + r w = 39 + 60 ) for data 0x01. the third connection is the next tap point, representing 177 (2 39 + 60 ) for data 0x02 and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 9961 (r ab C 1 lsb + r w ). figure 42 shows a simplified diagram of the equivalent rdac circuit where the last resistor string will not be accessed; therefore, there is 1 lsb less of the nominal resistance at full scale in addition to the wiper resistance. b rdac latch and decoder w a r s r s r s r s sd bit d7 d6 d4 d5 d2 d3 d1 d0 figure 42. ad5161 equivalent rdac circuit 1 the terms digital potentiometer, vr, and rdac are used interchangeably. the general equation determining the digitally programmed output resistance between w and b is w ab wb rr d dr ??? 256 )( (1) where d is the decimal equivalent of the binary code loaded in the 8-bit rdac register, r ab is the end-to-end resistance, and r w is the wiper resistance contributed by the on resistance of the internal switch. in summary, if r ab = 10 k and the a terminal is open circuited, the following output resistance r wb will be set for the indicated rdac latch codes. table 9. codes and corresponding r wb resistance d (dec.) r wb () output state 255 9,961 full scale (r ab C 1 lsb + r w ) 128 5,060 midscale 1 99 1 lsb 0 60 zero scale (wiper contact resistance) note that in the zero-scale condition a finite wiper resistance of 60 is present. care should be taken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between the wiper w and terminal a also produces a digitally controlled complementary resistance r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is w ab wa rr d dr ?? ? ? 256 256 )( (2) for r ab = 10 k and the b terminal open circuited, the following output resistance r wa will be set for the indicated rdac latch codes. table 10. codes and corresponding r wa resistance d (dec.) r wa () output state 255 99 full scale 128 5,060 midscale 1 9,961 1 lsb 0 10,060 zero scale typical device to device matching is process lot dependent and may vary by up to 30%. since the resistance element is processed in thin film technology, the change in r ab with temperature has a very low 45 ppm/c temperature coefficient.
ad5161 data sheet rev. b | page 16 of 20 programming the pote ntiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper - to - b and wiper - to - a proportional to the input voltage at a - to - b. unlike the polarity of v dd to gnd, which must be positive, voltage across a - b, w - a, and w - b can be at either polarity. if ignoring the effect of the wiper resistance for approximation, connecting the a terminal to 5 v and the b terminal to ground produces an output voltage at the wiper - to - b starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across terminal ab divided by the 256 positions of the potentiometer divider. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminals a and b is b a w v d v d d v 256 256 256 ) ( ? + = (3) for a more accurate calculation, which includes the effect of wiper resistance, v w , can be found as b wa a wb w v d r v d r d v 256 ) ( 256 ) ( ) ( + = (4) operation of the digital pote ntiometer in the divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors r wa and r wb and not the absolute values. therefore, the temperature drift reduces to 15 ppm/c. pin selectable digit al interface the ad5161 provides the flexibility of a selectable interface. when the digital interface select (dis) pin is tied low, the spi mode is engaged. when the dis pin is tied high, the i 2 c mode is en gaged. spi compatible 3 - wire serial bus (dis = 0) the ad5161 contains a 3 - wire spi compatible digital interface (sdi, cs , and clk). the 8 - bit serial word must be loaded msb first. the format of the word is shown in table 6 . the positive - edge sensitive clk input requires clean transitions to avoid clocking incorrect data into the serial input register. standard logic families work well. if mechanical switches are used for product evaluation, they should be debou nced by a flip - flop or other suitable means. when cs is low, the clock loads data into the serial register on each positive clock edge (see figure 37). the data setup and data hold times in the specification t able determine the valid timing requirements. the ad5161 uses an 8 - bit serial input data register word that is transferred to the internal rdac register when the cs line returns to logic high. extra msb bits are ignored. daisy - chain operation the serial data output (sdo) pin contains an open - drain n - channel fet. this output requires a pull - up resistor in order to transfer data to the next packages sdi pin. this allows for daisy - chaining several rdacs from a single processor serial data line. the pull - up resistor termination voltage can be larger than the v dd supply voltage. it is recommended to increase the clock period when using a pull - up resistor to the sdi pin of the following device because capacitive loading at the daisy - chain node sdo - sdi between devices may induce time delay to subsequent devices. users should be aware of this potential problem to achieve data transfer successfully (see figure 43 ). if two ad5161s are daisy - chained, a total of at least 16 bits of data is required. the first eight bits, complying with the format shown in table 6 , go to u2 and the second eight bits with the same format go to u1. cs should be kept low until all 16 bits are clo cked into their respective serial registers. after this, cs is pulled high to complete the operation and load the rdac latch. if the data word during the cs low period is greater than 16 bits, any additional msbs will be discarded. ad5161 ad5161 u2 c u1 cs sdi clk clk sdo cs clk sdi sdo sc mosi v dd r p 2.2k? figure 43 . daisy - chain configuration i 2 c compatible 2 - wire serial bus (dis = 1) the ad5161 can also be controlled via an i 2 c compatible serial bus with dis tied high. the rdacs are connected to this bus as sla ve devices. the first byte of the ad5161 is a slave address byte (see table 7 and table 8 ). it has a 7 - bit slave address and a r/ w bit. the six msbs of the slave address are 010110, an d the following bit is determined by the state of the ad0 pin of the device. ad0 allows the user to place up to two of the i 2 c compatible devices on one bus. the 2 - wire i 2 c serial bus protocol operates as follows: 1. the master initiates data transfer by esta blishing a start condition, which is when a high - to - low transition on the sda line occurs while scl is high (see figure 40 ). the following byte is the slave address byte, which consists of the 7 - bit slave address followed by an r/ w bit (this bit determines whether data will be read from or written to the slave device).
data sheet ad5161 rev. b | page 17 of 20 the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is te rmed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master will read from the slave device. on the other hand, if the r/ w bit is low, the master will write to the slave device. 2. a write operation contains an extra instruction byte that a read operation does not contain. such an instruction byte in write mode follows the slave address byte. the first bit (msb) of the instruction byte is a dont care. the second msb, rs, is the midscale reset. a logic high on this bit moves the wiper to the center tap where r wa = r wb . this feature effectively writes over the contents of the register, and thus, when taken out of reset mode, the rdac will remain at midscale. the third msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost 0 ? in rheostat mode or 0 v in potentiometer mode. it is important to note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previous setting will be applied to the rdac. also, during shutdown, new sett ings can be programmed. when the part is returned from shutdown, the corresponding vr setting will be applied to the rdac. the remainder of the bits in the instruction byte are dont cares (see table 7 ). 3. after acknowledging the i nstruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of s cl and remain stable during the high period of scl (see table 7 ). 4. in the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, where there are eight data bits followed by an acknowledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 41). 5. when all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low - to - high transition on the sda line while scl is high. in write mode, the master wil l pull the sda line high during the tenth clock pulse to establish a stop condition (see figure 40 ). in read mode, the master will issue a no acknowledge for the ninth clock pulse (i.e., the sda line remains high). the master will then bring the sda line low before the tenth clock pulse which goes high to establish a stop condition (see figure 41). a repeated write function gives the user flexibility to update the rdac output a number of times after addressi ng and instructing the part only once. during the write cycle, each data byte will update the rdac output. for example, after the rdac has acknowledged its slave address and instruction bytes, the rdac output will update after these two bytes. if another b yte is written to the rdac while it is still addressed to a specific slave device with the same instruction, this byte will update the output of the selected slave device. if different instructions are needed, the write mode has to start again with a new s lave address, instruction , and data byte. similarly, a repeated read function of the rdac is also allowed. readback rdac value the ad5161 allows the user to read back the rdac values in the read mode. refer to table 7 and table 8 for the programming format. multiple devices on one bus figure 44 shows two ad5161 devices on the same serial bus. each has a different slave address since the states of their ad0 pins are different. this allows each rdac within each device to be written to or read from independently. the master device output bus line drivers are open - drain pull - downs in a fully i 2 c compatible interface. master ad5161 sda scl r p r p +5v +5v sda scl sda scl ad5161 ad0 ad0 figure 44 . mu ltiple ad5161 devices on one i 2 c bus
ad5161 data sheet rev. b | page 18 of 20 level shifting for b idirectional interfa ce while most legacy systems may be operated at one voltage, a new component may be optimized at another. when two systems operate the same signal at two different voltages , proper level shifting is needed. for instance, one can use a 3.3 v e 2 prom to interface with a 5 v digital potentiometer. a level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be sto red to and retrieved from the e 2 prom. figure 45 shows one of the implementations. m1 and m2 can be any n - channel signal fets, or if v dd falls below 2.5 v, low threshold fets such as the fdv301n. e 2 prom ad5161 sda1 scl1 d g r p r p 3.3v 5v s m1 scl2 sda2 r p r p g s m2 v dd1 = 3.3v v dd2 = 5v d figure 45 . level shifting for operation at different potentials esd protection all digital inputs are protected with a series input resistor and parallel zener esd structures shown in figure 46 and figure 47. this applies to the digital input pins sdi/sda, clk/scl, and cs /ad0. logic 340? v ss figure 46 . esd protection of digital pins a,b,w v ss figure 47 . esd protection of resistor te rminals terminal voltage ope rating range the ad5161 v dd and gnd power supply defines the boundary conditions for proper 3 - terminal digital potentiometer operation. supply signals present on terminals a, b, and w that exceed v dd or gnd will be clamped by th e internal forward biased diodes (see figure 48 ). a v dd b w v ss figure 48 . maximum terminal voltages set by v dd and v ss power - up sequence since the esd protection diodes limit the voltage compliance at terminals a, b , and w (see figure 48 ), it is important to power v dd /gnd before applying any voltage to terminals a, b, and w; otherwise, the diode will be forward biased such that v dd will be powered unintentionally and may affect the rest of th e users circuit. the ideal power - up sequence is in the following order: gnd, v dd , digital inputs, and then v a/b/w . the relative order of powering v a , v b , v w , and the digital inputs is not important as long as they are powered after v dd /gnd. layout and pow er supply bypassing it is a good practice to employ compact, minimum lead length layout design. the leads to the inputs should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with disc or chip ceramic capacitors of 0.01 f to 0.1 f. low esr 1 f to 10 f tantalum or electrolytic c apacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see figure 49 ). note that the digital ground should also be joined remotely to the analog ground at one point to minim ize the ground bounce. ad5161 v dd c1 c3 gnd 10f 0.1f + v dd figure 49 . power supply bypassing
data sheet ad5161 rev. b | page 19 of 20 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 1 0 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 50 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters ordering guide model 1 , 2 r ab (?) temperature package description package option branding ad5161brm5 5k C 40c to +125c 10- lead msop rm - 10 d0c ad5161brm5 - rl7 5k C 40c to +125c 10- lead msop rm - 10 d0c ad5161brmz5 5k C 40c to +125c 10- lead msop rm - 10 d0c # ad5161brmz5 - rl7 5k C 40c to +125c 10- lead msop rm - 10 d0c # ad5161brm10 10k C 40c to +125c 10- lead msop rm - 10 d0d ad5161brm10 - rl7 10k C 40c to +125c 10- lead msop rm - 10 d0d ad5161brmz10 10k C 40c to +125c 10- lead msop rm - 10 d0d # ad5161brmz10 - rl7 10k C 40c to +125c 10- lead msop rm - 10 d0d # ad5161brm50 50k C 40c to +125c 10- lead msop rm - 10 d0e ad5161brm50 - rl7 50k C 40c to +125c 10- lead msop rm - 10 d0e ad5161brmz50 50k C 40c to +125c 10 - lead msop rm - 10 d0e # ad5161brmz50 - rl7 50k C 40c to +125c 10- lead msop rm - 10 d0e # ad5161b rm100 100k C 40c to +125c 10- lead msop rm - 10 d0f ad5161brm100 - rl7 100k C 40c to +125c 10- lead msop rm - 10 d0f ad5161brmz100 100k C 40c to +125c 10- lead msop rm - 10 d0f # ad5161brmz100 - rl7 100k C 40c to +125c 10- lead msop rm - 10 d0f # eval - ad5161ebz see note 2 evaluation board 1 z = rohs compliant part, # denotes rohs compl iant part may be top or bottom marked. 2 the eval - ad5161ebz evaluation board is shipped with the 10 k? r ab resistor option; however, the board is compatible with all available resistor value options. the ad5161 contains 2532 transistors. die size: 30.7 mil 76.8 mil = 2358 sq. mil.
ad5161 data sheet rev. b | page 20 of 20 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies co nveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2003 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d03435 - 0- 8/12(b)

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